Job Description
Elevate your career as an ASIC Verification Senior Engineer at Synopsys. Utilize your skills in SystemVerilog and UVM to push the boundaries of memory interface technology in a dynamic team.
As a senior staff engineer, you will focus on developing verification strategies for cutting-edge memory interface IP. Your responsibilities include creating effective test plans, implementing UVM testbench infrastructure, and collaborating extensively with implementation teams. Your problem-solving aptitude and strong debugging skills will be key to overcoming verification challenges. Additionally, you will nurture the next generation of engineers by sharing your knowledge in a collaborative way.
Key Responsibilities:
• Implement verification test plans for memory interface IP
• Develop UVM testbenches for RTL PHY firmware verification
• Conduct technical reviews with cross-functional teams
• Resolve complex verification issues using debugging tools
• Coach junior engineers to...
As a senior staff engineer, you will focus on developing verification strategies for cutting-edge memory interface IP. Your responsibilities include creating effective test plans, implementing UVM testbench infrastructure, and collaborating extensively with implementation teams. Your problem-solving aptitude and strong debugging skills will be key to overcoming verification challenges. Additionally, you will nurture the next generation of engineers by sharing your knowledge in a collaborative way.
Key Responsibilities:
• Implement verification test plans for memory interface IP
• Develop UVM testbenches for RTL PHY firmware verification
• Conduct technical reviews with cross-functional teams
• Resolve complex verification issues using debugging tools
• Coach junior engineers to...