Job Description
Position : Design Engineer
Experience : 3 7 Years
Location : Bangalore
Notice Period : immediate / 15 Days NP
Skillset Required:
- Proficient in RTL Verification using SystemVerilog (SV) and UVM.
- Strong knowledge of FPGA Design Flow using VHDL as the RTL language.
- Hands-on experience in developing SV/UVM verification environments.
- Experience with Questa, Modelsim, or similar advanced simulation tools.
- Familiarity with the DO-254 verification process is a strong plus.
Key Responsibilities:
- Develop tests and test environments using SystemVerilog UVM for ...