Job Description
Why Join UsDefine detailed verification plans for blocks and systems Lead the verification activities in smaller sub-teams Develop SystemVerilog/UVM environments for blocks and top-level SoCs Debug functional errors in RTL Support younger engineers on their activities What You’ll Need Minimum BS/MS in Electrical Engineering or related technical field At least 8 years of digital verification experience Solid understanding of verification best practices such as verification planning, r...
We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.
What You’ll Do