Description
:
What candidate will Be Doing:
At-least6+ years of experienceinSystem Verilog HVL and C++/CAt-least 6+ year of experience inUVM.Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.Proficient inSVTB/UVM, C++ testbenchUnderstand DSP is a plusSubversion for Repository and Bugzilla is also a PlusProficient in debugand assertions codingVerification closure with teamWhat We Are Looking For:
At-least 6+ years of experienceinSystem Verilog HVL and C++/CAt-least 6+ year of experience inUVM.Make/Perl/Python / any scriptAny protocol experiace is fineEnsur...