Job Description
- Work with front -end team, DFT, and cross -functional teams to provide the solutions and make sure DFT DRCs are fixed
- Generating high -quality manufacturing ATPG test patterns for (SAF) stuck -at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on -chip test compression techniques.
Requirements
- BE/ BTech/ MTech/MS/ PhD in Electronics, Electrical, Computer Engineering or Computer Science Engineering with years of exp.
- Highly motivated and driven to face challenging design and debug problems
- In -depth knowledge and hands -on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis.
- Analyze the design and propose the best compression technique.
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