Digital Design Verification Engineer

Responsibilities:

• Verify Hardware/ASIC designs using UVM/SystemVerilog or Verilog language
• Design and implement verification environment and components
• Define and implement testcases
• Perform block-level and system-level simulation and debugging
• Perform regression testing and coverage analysis
• Create and maintain verification specifications and other technical documents
• Work closely with the team to understand project requirements and deliverables

Qualifications:

• Electronics/Computer Engineering degree major in microelectronics
• Experience in Hardware/ASIC verification cycle
• Experience in EDA tools for Hardware/ASIC verification
• Experience in scripting is a plus
• Knowledge in standards such as AMBA, PCIe, USB is a plus
• Good understanding of code versioning tools
• Goal oriented, self-organized, and independent