Job Description
Purpose:
We are seeking a highly skilled and motivated IO Design Expert with deep experience in designing GPIOs, specialty analog/digital IOs, and ESD protection circuits across technology platforms ranging from BCD technologies (e.g., 180nm/130nm/55nm) to advanced CMOS nodes (e.g., 28nm, 16nm, 12nm, 7nm, 5nm). You will play a critical role in the architecture, schematic design, layout oversight, simulation, verification, and qualification of IO libraries for complex So Cs with stringent reliability and performance requirements.
Areas Of Responsibility:
Architect and design a wide range of IO cells:
General Purpose IOs (GPIOs)
High-Speed IOs (LVDS, CML, SSTL, HSTL, etc.)
Power IOs (e.g., VDD, VSS pads)
Analog IOs for sensor interfaces, ADC/DAC connections
ESD protection devices and clamps (CDM, HBM, MM compliance)
High-voltage tolerant IOs (for BCD technologies)
Collaborate with system architects and package designers to define pad ring structure, signal a...
We are seeking a highly skilled and motivated IO Design Expert with deep experience in designing GPIOs, specialty analog/digital IOs, and ESD protection circuits across technology platforms ranging from BCD technologies (e.g., 180nm/130nm/55nm) to advanced CMOS nodes (e.g., 28nm, 16nm, 12nm, 7nm, 5nm). You will play a critical role in the architecture, schematic design, layout oversight, simulation, verification, and qualification of IO libraries for complex So Cs with stringent reliability and performance requirements.
Areas Of Responsibility:
Architect and design a wide range of IO cells:
General Purpose IOs (GPIOs)
High-Speed IOs (LVDS, CML, SSTL, HSTL, etc.)
Power IOs (e.g., VDD, VSS pads)
Analog IOs for sensor interfaces, ADC/DAC connections
ESD protection devices and clamps (CDM, HBM, MM compliance)
High-voltage tolerant IOs (for BCD technologies)
Collaborate with system architects and package designers to define pad ring structure, signal a...