Looking for DFT Leaders and Experts

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we have a role that will challenge and grow your skills in advanced silicon testing. Core Responsibilities You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery. Key focus areas include: Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC. Block level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization. Verification: Handling Pattern simulations (both Timing and Non-timing). SOC Integration: Pattern Retargeting to SOC/Subsystem levels and performing full-chip simulations. Memory & IP Test: Integration and simulation of MBIST, IJTAG, and Boundary Scan (JTAG). Debug & Analysis: Independent debugging of DFT simulations and netlist handling. Technical Requirements...

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