Job Description
Job Description:
Pay Range: $90hr - $100hr
Responsibilities:
Perform static timing analysis (STA) for the PCIe subsystem within the Sparta architecture. Develop, validate, and maintain PCIe-specific timing constraints (SDC) and exceptions. Run full‐chip and block‐level STA for PCIe paths across PVT corners and operating modes. Identify timing violations and drive ECO recommendations to close setup/hold, DRV, and noise issues. Collaborate with RTL, synthesis, PnR, and verification teams to ensure end‐to‐end PCIe timing signoff. Analyze clocking, resets, CDC paths, and PHY interface timing for PCIe. Generate timing reports and signoff documentation for program milestones. Support timing debug during subsystem integration and final tape‐out. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or related field. ...