Remote Digital Verification Engineer – SystemVerilog & C

A leading engineering firm based in Spain is seeking a Digital Verification Engineer for a remote opportunity. The role involves conducting functional verification and working with SystemVerilog and UVM methodology. Candidates should have strong proficiency in C and preferably experience with simulation tools like Questa. The company offers a competitive salary, a permanent contract, private healthcare, and opportunities for personal development while working on innovative projects within a global context.
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