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Job Description
DFT specifications, architecture and implementation using state-of-the-art methodologies and toolsMethodology support, DFT Flow Automation, and DFT InnovationSupport all product lines with High Coverage, Low Power, Low Test TimeDeliver high quality, verified, Automatic Test Pattern Generation (ATPG) patternsPre/Post silicon verification & debugWork independently and mentor junior team membersMinimum Qualifications
6 - 8 years of directly related experience in ASIC/SoC DFTExpert level knowledge of DFT architecture and planningHands on Tessent DFT Tool experienceExpert level knowledge of Scan, Test Compression, At-Speed Test, Memory Built-In Self-Test (MBIST), Logic Bist (LBIST)Hands-on experience of Scan Insertion, Compression Insertion...