Soc Verification Engineer — Uvm, Coverage, Sign-Off

A leading technology company is seeking a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks in Guadalajara, Mexico.
This role includes developing UVM testbenches, collaborating with engineering teams, and ensuring coverage closure.
The ideal candidate will have 5+ years of experience in design verification and expertise in UVM/SystemVerilog, with a focus on delivering high-quality silicon on schedule.
The position requires on-site presence and offers an exciting opportunity to contribute to cutting-edge technology.
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