Staff HSIO/DDR Bench Test Engineer

Engineering Group > Hardware Engineering

This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip). The role focuses on defining and executing test methodologies and characterizing high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, MIPI(DSI,CSI), PLLs and other proprietary interfaces. Responsibilities include developing and executing characterization plans to optimize design parameters and validate electrical compliance, driving corresponding first‑silicon bring‑up and debug to qualify designs fabricated at external foundries, and performing technical data analysis of parametric performance over various operating conditions and configurations. The engineer will also assist in hardware design and debug of PI and SI issues related to package and board design, and work closely with cross‑functional teams such...